1. Field of the Invention
The present invention relates to a technique for transferring data from a memory, and more particularly to a data transfer technique used for a memory device testing apparatus.
2. Description of Related Art
FIG. 1 shows a conventional configuration for transferring a fail signal stored in a failure analysis memory unit 10 to a memory failure remedy analysis unit 30 in a memory device testing apparatus to remedy a fail memory device.
The failure analysis memory unit 10 has a data storage memory 12, an address generation control unit 14, an address pointer 16, a multiplexer 18, and a data storage memory register 20. The memory failure remedy analysis unit 30 has a fail buffer memory 34 and an address pointer 36. When a defective cell is present in the memory device, a fail signal 91 which indicates the content of the failure is stored in an address in the data storage memory that corresponds to the address signal 65 of the defective cell of the test memory device. The address signal 65 passes through the input terminal on the 0-side of the multiplexer 18 and is input to the data storage memory 12. The data storage memory 12 has the same memory capacity as the memory device being tested.
The address pointer 16 outputs an address signal incremented by a clock signal. The address signal generated by the address pointer 16 passes through the input terminal on the 1-side of the multiplexer 18, and is input to the address pin of the data storage memory 12. In this case, a read request signal is input to the control pin of the data storage memory 12. As a result, the data containing the fail signal stored in the data storage memory 12 is read and transferred by the memory failure remedy analysis unit 30.
The address pointer 36 of the memory failure remedy analysis unit 30 receives substantially the same clock signal as the clock signal input to the address pointer 16. The address pointer 36 generates an address signal that accesses the fail buffer memory 34. This address signal is incremented by a click signal. The address signal generated by the address pointer 36 and the transfer data signal 22 output from the data storage memory 12 are input in synchronization to the fail buffer memory 34. A write request signal is input to the control pin of the fail buffer memory 34. The transfer data signal 22 is written onto the address designated by the address signal input from the address pointer 36 to the fail buffer memory 34. The data storage memory register 20 stores the value of the end address of the data storage memory 12. The address generation control unit 14 compares the value incremented by the address pointer 36 with the value stored in the data storage memory register 20. When the value incremented by the address pointer 36 agrees with the value stored in the data storage memory register 20, all the data inside the data storage memory 12 is transferred. In this case, the transfer operation is completed. After this, the address pointers 16 and 36 are reset and returned to the initial states.
In the conventional configuration shown in FIG. 1, regardless of the number of defective cells, all the data in the data storage memory 12 from the start address to the end address must be transferred. For example, when it takes Tread (sec) to read the data stored in 1 address and the address of the test memory device has the length of 64M words, it takes 64M×Tread (sec) to transfer all the data stored in the data storage memory 12. Hence, as the capacity of the test memory device such as a DRAM, SDRAM or the like is increased, the length of time required to transfer all the data from the failure analysis memory unit 10 to the memory failure remedy analysis unit 30 is increased accordingly.